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→Le 74HC138
== Le 74HC138 ==
== Le 74HC138 ==
The 74HC138; 74HCT138 is a '''high-speed''' Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1
and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7).
The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 and E2) and
one active HIGH (E3). Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138
to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one
inverter.
[[Fichier:df.mchobby.be/datasheet/74HC_HCT138.pdf Fiche technique]] (''NXP.com, pdf, anglais'')
== Montage ==
== Montage ==