Modifications

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588 octets ajoutés ,  2 juillet 2015 à 20:53
Ligne 182 : Ligne 182 :  
| I/O pin capacitance ||CIO ||||||5 ||||pF
 
| I/O pin capacitance ||CIO ||||||5 ||||pF
 
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{{underline|Notes:}}
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[1] FT = Five-volt tolerant. In order to sustain a voltage higher than V3V3+0.3 the internal pull-up/pull-down resistors must be disabled.
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[2] Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
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[3] With a minimum of 100mV.
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[4] Leakage could be higher than max. if negative current is injected on adjacent pins.
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[5] Pull-up and pull-down resistors are designed with a true resistance in series with switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order).
    
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